1. Field of the invention
The present invention relates to a semiconductor device, particularly a capacitor formed in a semiconductor device. For example, the present invention is concerned with an improvement of a memory capacitor in a dynamic random access memory (hereinafter referred to as "DRAM") having a memory cell comprising one transistor and one capacitor.
2. Description of the Background Art
As one of passive elements constituting a semiconductor integrated circuit there is a capacitor, which is a basic and important element in circuit configuration. Generally, a capacitor is constituted by sandwiching a dielectric film sideways in between two electrode layers, and is electrically charged by applying a voltage across those electrode layers. The amount of an electric charge capable of being stored in the capacitor, namely, capacitance, is proportional to the opposed area between the electrodes and inversely proportional to the thickness of the dielectric film. The present technical advancement, in one direction thereof, aims at increasing capacitance by thinning the dielectric film and using a material of a large dielectric constant.
A DRAM (Dynamic Random Access Memory) is one example of a semiconductor integrated circuit using a capacitor. The structure of a memory cell in a DRAM having a capacitor is shown in Japanese Patent Laying-Open No. 66065/1981 (hereinafter referred to as the prior art literature 1). FIG. 10 illustrates a sectional structure of the memory cell of the DRAM shown in the prior art literature 1. The memory cell includes one MOS (Metal Oxide Semiconductor) type field effect transistor and one capacitor. MOS type field effect transistor is provided with an n.sup.+ impurity region 7 formed in a semiconductor substrate 1 and a gate electrode 6 formed on the surface of the semiconductor substrate 1 through a gate insulating film 5. The gate electrode 6 is formed of polycrystalline silicon. The capacitor has an n-type impurity region 4a formed in the semiconductor substrate 1, a dielectric layer 3 formed on the surface of the n-type impurity region and an upper electrode 4b formed on the surface of the dielectric layer 3. The upper electrode 4b is formed of polycrystalline silicon. The dielectric layer 3 is of a three-layer structure wherein a silicon nitride film 8 is sandwiched in between silicon oxide films 9 and 20. Adjacent memory cells are isolated from each other by a field insulating layer 2.
The memory cell in the DRAM performs a storing operation by making information corresponding to the presence or absence of an electric charge stored in the capacitor. Therefore, the capacitor is required to hold capacitance in an amount not smaller than a predetermined amount.
On the other hand, the following are mentioned as prior art literatures giving consideration to the characteristics of the capacitor dielectric layer under the aforementioned background;
(1) Japanese Patent Publication No. 770/1985 (the prior art literature 2, hereinafter).
(2) "Breakdown Characteristics of 30P-c-4 SiO.sub.2 /Si.sub.3 N.sub.4 Double-layer Film" (A paper of the Japanese Society of Applied Physics, Mar. 28, 1987, P. 557) the prior art literature 3, hereinafter).
(3) "TDDB Characteristics in 19P-N-3 MONOS Structure" (A paper of the Japanese Society of Applied Physics, Oct. 17, 1987, P. 570) (the prior art literature 4, hereinafter).
(4) "Inter-Poly SiO.sub.2 /Si.sub.3 N.sub.4 Capacitor Films 5 nm Thick for Deep Submicron LSIs" (Extended Abstracts of the 20th (1988 International) Conference on Solid State Devices and Materials, Tokyo, 1988, pp. 173-176) the prior art literature 5, hereinafter).
(5) "Reliability of nano-meter thick multi-layer dielectric films on polycrystalline silicon" (25th annual proceedings of reliability physics, 1987) (the prior art literature 6, hereinafter).
In the prior art literature 2, it is described that storage capacitance is formed on the sidewalls of a groove formed in a silicon substrate and that an insulating film of the storage capacitance is formed as a three-layer insulating film comprising silicon dioxide, silicon nitride and silicon dioxide layers, the total film thickness being 20 nm (200.ANG.). However, the thickness of each constituent layer of the three-layer structure is not shown therein.
In the prior art literature 3, it is described that in an MIS capacitor using an SiO.sub.2 /Si.sub.3 N.sub.4 film as an insulating film, the life of a double-layer film having a thin oxide film is long. Oxide films 20.ANG. and 40.ANG. in thickness, respectively, are shown therein.
In the prior art literature 4, it is disclosed that intrinsic time of breakdown becomes longer as the upper oxide film becomes thinner in an NONOS capacitor employing an ONO(Oxide-Nitride-Oxide) film as an insulating film. The thickness of the lower oxide film is 40.ANG. and the thickness of the nitride film is 90.ANG.. However, the thickness of the upper oxide film is not shown.
In the prior art literature 5, the life of a capacitor employing silicon dioxide and silicon nitride are used as an insulating films is made longer when the oxide film has the thickness of 2 nm (20.ANG.) than when the oxide film is 0 nm.
In the prior art literature 6, it is said that the thickness of the upper oxide film must be as thin as possible so long as it prevents leak current, in a capacitor employing silicon dioxide and silicon nitride. Oxide films having the thickness of 20.ANG. and 40.ANG. are disclosed as examples.
On the basis of the aforementioned prior art literature the present inventors produced two capacitors each having an insulating layer of a three-layer structure comprising silicon dioxide, silicon nitride and silicon dioxide layers, one capacitor having an upper silicon dioxide layer 20.ANG. in thickness and the other 40.ANG., and tested Time Dependent Dielectric Breakdown characteristic (hereinafter referred to as "TDDB characteristic"). But both capacitors were inferior in TDDB characteristic and their reliability as capacitors was poor. From this fact it is presumed that in the capacitor having a silicon dioxide film thickness of 40.ANG., if it is used for a long time under the application of voltage between both electrodes of the capacitor, electrons will be accumulated in the silicon oxide film 10, resulting in deterioration of the film, leading to dielectric breakdown of the insulating layer 3.
In the capacitor having a silicon dioxide film thickness of 20.ANG., because of such a small silicon dioxide film thickness, it is presumed that the nitride film will involve various defects, thus causing dielectric breakdown.
More particularly, in case of a thin nitride film, various defective portions are apt to occur in the nitride film at the time of deposition. The upper silicon dioxide film acts to remedy such defects of the nitride film. However, if this silicon dioxide film is thin, its defect remedying function will be unsatisfactory, thus allowing the defective portions to remain in the nitride film.